Abstract: This paper presents the current status of DUV photolithography manufacturing for 0.5- and sub-0.5-micrometer CMOS devices. For the manufacturing toolset and process described, the throughput and exposure performance progressed from an early development stage of less than 100 wafers per toolset per day, to greater than 300 wafers per toolset per day. This improvement was achieved in less than nine months. The DUV cost of ownership, in comparison to existing 0.5-micrometer i-line technologies, drove high DUV throughput requirements at minimized chemical usage. The increased output of this complex cluster/process was achieved by concentrating on the key detractors: tool reliability, coating defects, overlay and critical dimension rework, and manufacturing efficiency. These four detractors, and the corrective actions, are described in this paper. Work continues to progress in tool reliability, process stability, implementation of automated systems, and manufacturing procedures. In addition, this manufacturable DUV technology is being extended to 0.35- micrometer applications with both the current tool set and higher numerical aperture (NA) step-and-scan exposure tools. !6
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