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An investigation into Scalability and Compliance for Triple Patterning with Stitches for Metal 1 at the 14nm node

机译:在14nm节点上对金属1的针迹进行三重图案化的可扩展性和合规性研究

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Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node's metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance - the task of finding a 3-color mask decomposition for a design - is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10's of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.
机译:光刻专家希望通过EUV光刻技术在20nm节点上实现单图案化。但是,由于EUV准备工作的延迟,当前需要采用193i光刻技术进行双图案化才能批量生产20nm节点的金属1层。在14nm甚至可能在10nm节点,LE-LE-LE三重构图技术(TPT)是构图局部互连和金属1层的首选方法之一。尽管以前的研究集中在接触掩模的TPT上,但是金属层带来了新的挑战和机遇,特别是能够分解多个掩模上的设计多边形的能力。第三掩模提供的额外灵活性以及利用多边形缝合的能力均有助于提高顺应性。但是,确保TPT的合规性(为设计寻找3色掩模分解的任务)仍然是一项艰巨的任务。此外,可扩展性问题使三重图案分解的难度倍增,这是一个NP完全问题。确实,先前的工作表明,数千个节点或多边形以上的网络大小开始需要花费更长的时间才能进行计算[3],这使得针对任意布局进行全芯片分解是不切实际的。在实践中,金属1布局可以视为两个独立的问题域,即:标准单元的分解和IP块的分解。标准单元通常只包含几个10的多边形,并且应该可以快速分解。连续的设计迭代应解决合规性问题并提高包装密度。多次放置标准像元后,密度的提高会倍增。另一方面,IP块可能涉及非常大的网络。本文评估了金属1层的三重图案分解的多种方法。权衡多边形缝合的好处,尤其是解决常见的不符合要求的布局配置并提高包装密度的能力,与寻找优化的合法分解以及应对日益增加的可扩展性挑战的难度增加相权衡。

著录项

  • 来源
    《Optical microlithography XXVI》|2013年|868308.1-868308.11|共11页
  • 会议地点 San Jose CA(US)
  • 作者单位

    Synopsys SARL, 12 Rue Lavoisier, 38330 Montbonnot, France;

    Synopsys, 700 E. Middlefield Rd., Mountain View, CA, USA 94043;

    Synopsys, 700 E. Middlefield Rd., Mountain View, CA, USA 94043;

    Synopsys, 700 E. Middlefield Rd., Mountain View, CA, USA 94043;

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  • 正文语种 eng
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