A model for enhanced manufacturability of defect tolerantintegrated circuits

摘要

Many factors contribute the the cost of manufacturing integratedncircuits. These include the yield of the design IC, the complexity ofnits testing, the packaging cost, etc. and they all must be taken intonaccount when designing a defect tolerant integrated circuit. The authorsnpresent a mathematical model which includes all major factorsncontributing to the cost of manufacturing ICs. This model allows thendetermination of the design which maximizes the expected profit rathernthan maximizing the yield. Numerical examples illustrating the proposednmodel are also presented