Neuroprocessor NeuroMatrix NM6403 architectural overview

摘要

Abstract: The paper represents an architecture overview of the NeuroMatrix NM6403 neuroprocessor designed for 32-bit and 64-bit data processing. The paper includes brief description of the neuroprocessor pinout, structure and functional units. The neuroprocessor comprise original RISC core, vector coprocessor (VCP) and some peripheral units. RISC core provides general control functions, 32-bit program and data address generation, 32-bit arithmetic, logic and shift operations. The main neuroprocessor operational unit is VCP, applied for variable bit-length vector data arithmetic, logic and saturation operations. The base VCP operation is matrix by vector multiplication with accumulation. Each data vector is a 64-bit word of packed data word. It is formed by set of variable bit length operands with user defined bit length in a range from 1 to 64 bits. Neuroprocessor includes two external 64-bit buses. The programmable memory interface units allow to use static or dynamic memory having wide range of time parameters without external controller. The neuroprocessor support shared memory mode for each of the external buses. With conjunction of two byte width communication ports this one makes it easy to design multiprocessor systems. Also this paper represents addressing modes, instruction set, supported interrupts. The neuroprocessor is designed using CMOS 0.5 $mu@m technology, power supply voltage is 3.3 V, clock rate is 50 MHz with one instruction per clock cycle performance.!2