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Adaptive Gain, Equalization, and Wavelength Stabilization Techniques for Silicon Photonic Microring Resonator-Based Optical Receivers

机译:基于硅光子微环谐振器的光接收机的自适应增益,均衡和波长稳定技术

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Interconnect architectures based on high-Q silicon photonic microring resonator devices offer a promising solution to address the dramatic increase in datacenter I/O bandwidth demands due to their ability to realize wavelength-division multiplexing (WDM) in a compact and energy efficient manner. However, challenges exist in realizing efficient receivers for these systems due to varying per-channel link budgets, sensitivity requirements, and ring resonance wavelength shifts. This paper reports on adaptive optical receiver design techniques which address these issues and have been demonstrated in two hybrid-integrated prototypes based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. A 10Gb/s power-scalable architecture employs supply voltage scaling of a three inverter-stage transimpedance amplifier (TIA) that is adapted with an eye-monitor control loop to yield the necessary sensitivity for a given channel. As reduction of TIA input-referred noise is more critical at higher data rates, a 25Gb/s design utilizes a large input-stage feedback resistor TIA cascaded with a continuous-time linear equalizer (CTLE) that compensates for the increased input pole. When tested with a waveguide Ge PD with 0.45A/W responsivity, this topology achieves 25Gb/s operation with -8.2dBm sensitivity at a BER=10~(-12). In order to address microring drop filters sensitivity to fabrication tolerances and thermal variations, efficient wavelength-stabilization control loops are necessary. A peak-power-based monitoring loop which locks the drop filter to the input wavelength, while achieving compatibility with the high-speed TIA offset-correction feedback loop is implemented with a 0.7nm tuning range at 43μW/GHz efficiency.
机译:基于高Q硅光子微环谐振器器件的互连架构,由于能够以紧凑且节能的方式实现波分复用(WDM),因此能够满足数据中心I / O带宽需求的急剧增长,提供了一种有前途的解决方案。然而,由于每信道链路预算,灵敏度要求和环形谐振波长偏移的变化,在为这些系统实现有效的接收机方面存在挑战。本文报道了解决这些问题的自适应光接收机设计技术,并已在两个混合集成的原型中得到了证明,这些原型基于在130nm SOI工艺中实现的微环滴滤光片和波导光电检测器以及在65nm CMOS中设计的高速光学前端。 10Gb / s功率可缩放架构采用了三个反相器级跨阻放大器(TIA)的电源电压缩放功能,该放大器与眼图监控器控制环路相匹配,可为给定通道提供必要的灵敏度。由于在更高数据速率下降低TIA输入参考噪声更为关键,因此25Gb / s设计采用了一个大型输入级反馈电阻TIA,该电阻级联了一个连续时间线性均衡器(CTLE),以补偿增加的输入极点。当使用具有0.45A / W响应度的波导Ge PD进行测试时,该拓扑在BER = 10〜(-12)时以-8.2dBm的灵敏度实现25Gb / s的操作。为了解决微环滴滤器对制造公差和热变化的敏感性,需要有效的波长稳定控制环路。基于峰值功率的监视环路可将滤光片锁定在输入波长,同时实现与高速TIA失调校正反馈环路的兼容性,并具有0.7nm调谐范围,效率为43μW/ GHz。

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