Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS

摘要

Photonic interconnects are a promising technology to meet the bandwidth demands of next-generation high-performance computing systems. This paper presents silicon photonic transceiver circuits for a microring resonator-based optical interconnect architecture in a 1 V standard 65 nm CMOS technology. The transmitter circuits incorporate high-swing ( $2{rm V}_{{rm pp}}$ and $4{rm V}_{{rm pp}})$ drivers with nonlinear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 Gb/s operation, the $4{rm V}_{{rm pp}}$ transmitter achieves 12.7 dB extinction ratio with 4.04 mW power consumption, excluding laser power, when driving wire-bonded modulators designed in a 130 nm SOI process, while a 0.28 nm tuning range is obtained at 6.8 $mu$ W/GHz efficiency with the bias-based tuning scheme implemented with the $2{rm V}_{{rm pp}}$ transmitter. When tested with a wire-bonded 150 fF p-i-n photodetector, the receiver achieves ${-}$ 9 dBm sensitivity at a ${rm BER}=10^{-9}$ and consumes 2.2 mW at 8 Gb/s. Testing with an on-die test structure emulating a low-capacitance waveguide photodetector yields 17 $mu$A$_{{rm pp}}$ sensitivity- at 10 Gb/s and more than 40% power reduction with higher input current levels.