Field programmable gate array based reconfigurable preprocessor

摘要

Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools which can work with user-definable macros. Ongoing work in the areas of partitioning, synthesis, placement, packaging and compilation will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U/spl times/160 slave board with two high-speed reconfigurable parallel interfaces. In order to allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of the CHAMP design process. As a verification of the CHAMP technology, an advanced IR missile warning application was mapped onto the CHAMP architecture achieving greater than 1 billion operations/sec of real-time throughput while utilizing 75% of the CHAMP board's processing resources.