FPGA-based emulation has emerged as an important tool in the overall validation process for an increasing number of large integrated circuits. Emulation gives the ability to validate a design using long-running, realistic tests, which are infeasible to perform using simulation. Traditionally, however, FPGA-based emulation has been used to validate only the functional behavior of an integrated circuit, since circuit-level properties (e.g., timing, noise margins, etc.) are obviously different between the FPGA emulation and the final integrated circuit. In this paper, we show that emulation can also be used as an important tool to assist validation of more than just functional behavior. In particular, we show how FPGA-based emulation can be used to evaluate the critical-path timing coverage of a validation plan, and show that the area and timing overheads are acceptable. We demonstrate this technique to measure the critical-path coverage of a complex SoC using common postsilicon validation tests — including booting Linux, and running targeted and random programs — giving valuable insight into the quality of such tests in covering the timing paths in a design post-silicon.
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