A 6F~2 Buried Wordline DRAM Cell for 40nm and Beyond

摘要

We present a 46nm 6F~2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013um~2 published to date. The TiN/W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30nm without compromising its performance.