A little DFT goes a long way when testing multi-Gb/s I/O signals

摘要

Manufacturing test equipment used to test multi-Gb/s input/output signals is typically expensive, and costs are expected to rise dramatically as data rates on these signals get even faster. The problem is further exacerbated by a rapid increase in the number of chip pins dedicated to interfaces that require such high-speed signals. Many recent interface specification standards for SERDES, PCI Express, USB, DDR, SATA, etc. demand performance parameters that seem nearly impossible to test in a high volume manufacturing (HVM) test environment. Adaptive design techniques, ECC, proper characterization, and a well-balanced system design approach using DFT in harmony with practical fixturing and ATE configurations can provide a cost-effective environment for economical manufacturing test of multi-Gb/s I/O signals.