Design and Analysis of a Gilbert Analog Multiplier for Input Dynamic Range optimization

摘要

In this paper, the design of a Gilbert analog multiplier is presented from design equations for input dynamic range optimization to measurement results, these last being obtained in the context of a square function dedicated to analog signal processing. The full circuit has been implemented using an AMS $0.35mu m$ technology with a voltage supply (VDD) of 3.3V. Assuming a differential input voltage of $+/-400mV$ with a common voltage of VDD/2, it is able to compute the square value of its differential input voltage with a mean precision of 2.92% in $5mu s$. Finally, the analog multiplier itself has a core area of $620mu m^{2}$ and offers power-gating capability, which enables a power consumption of $2.28mu W$ when a duty cycle of 0.25% is considered.