A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems

摘要

Increasingly, multi-core architectures are proposed and multiprocessor systems are also realized within the FPGA. The communication mechanisms among devices are fundamental and influence the feasibility and performance of the system. The main ones can be based on the bus, on shared memory, or on NoC. The preferred communication, for versatility and ease of programming, is via a shared memory, which, in fact, you want to imitate in different ways. But a true multiport memory that allows simultaneous access to the same locations, has various manufacturing difficulties. In this contribution, the method that we use, to make the shared memory feasible and practically usable, is a targeted configuration of its structure. With a parameterization in FPGA of memory we want to adapt the architecture of communication to the communication needs of the multiprocessor system. So the idea is to try to reduce the required interconnections to share the memory locations among all processors, limiting them strictly to the operational needs of the application. We show the results achieved with implementations in FPGA comparing the occupation of the area and the required resources, trying to figure out if this, which happens to be an even non-trodden path, can lead to viable solutions to current and future needs of multiprocessor communication.