Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

摘要

Accurate MOSFET I/sub dsat/ model including LDD parasitic resistance and channel subthreshold leakage models current MOSFET operation regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, have been presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines have been discussed in terms of device T/sub ox/, V/sub dd/ and V/sub t/. It predicts that there exists certain T/sub ox/ value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying V/sub dd/, T/sub ox/ and V/sub t/ are highlighted.