Design and performance analysis of RAM_RD_CONTROL module using Xilinx ISE 14.2

摘要

RAM_Read_Control module is designed to control the data read operation to the Random Access Memory (RAM) core. The RAM core is used for saving the raw data in impedance measurement module of Electrical Impedance Tomography (EIT) system, KHU Mark 2.5. The performance of this module is analyzed using XILINX ISE 14.2 design tool on Virtex-5 (xc5vlx20t-ff323) chip. The performance analysis is done for different I/O Standards. HSTL (high speed transceiver logic-I, II, III, IV), LVCMOS15 (low voltage metal oxide semiconductor) and LVTTL (low voltage transistor-transistor logic) I/O standards are used to analyze the performance on Virtex-5 FPGA. This analysis is done at operating frequencies of 400MHz, 500 MHz, 600 MHz and 700 MHz. It is observed that when LVCMOS15 performance results are compared with LVTTL, HSTL_I, II, III, IV at 500MHz, 600MHz, and 700MHz we obtain 65.3%, 65%, 64.5% power reduction respectively. The minimum power reduction is obtained at 700 which are 64.5% when we compared LVCOMS15 with HSTL_IV I/O standard.