CLAHE implementation on a low-end FPGA board by high-level synthesis

摘要

Automobile companies have been trying to replace side mirrors of cars with small cameras for reducing air resistance. It enables us to apply some image processing for improving quality. This paper describes a design of Contrast Limited Adaptive Histogram Equalization (CLAHE), which improves the quality of the dark image for the side mirror camera, on a low-end FPGA board by high-level synthesis. By constituting CLAHE as a data flow design flow, we could achieve performance comparable to the implementation with HDL. The code is parameterized so that the number of tiles and the size of the image can be easily changed. The source code for this research can be downloaded from https://github.com/kokihonda/fpga_clahe.