In this paper, we propose a counterexample-guided diagnosis approach to identify faults in circuit designs described as net-lists on the gate-level. Given a faulty net-list and a logic specification of the correct, intended behavior of the circuit, the diagnosis algorithm iteratively computes the exact set of fault candidates, i.e., a subset of the circuit's gates at which all counterexamples can be rectified. The algorithm equips SAT-based diagnosis with systematic counterexample generation. In each iteration, an over-approximation of the fault candidates is computed and a new counterexample is generated such that at least one of the fault candidates can be excluded in the next iteration. The algorithm terminates if no such counterexample exists and no remaining fault candidate can be excluded. The number of counterexample generated is not minimal and, thus, we additionally provide a counterexample reduction algorithm to post-process the set of generated counterexamples and obtain some insight in how many counterexamples are sufficient to exactly pinpoint a fault. We evaluate counterexamples-guided diagnosis for a set of benchmark circuits and provide a comparison to an exact algorithm that uses a state-of-the-art QSAT oracle. The accuracy of both algorithms is per design equal, whereas counterexample-guided diagnosis significantly outperforms the QSAT-based diagnosis algorithm.
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