Realization and Synthesis of Ring Counter and Twisted Ring Counter using Reversible Logical Computation with Minimum Quantum Cost

摘要

Reversible Logical computation is the dominating field of research in low power VLSI. In recent time reversible logic has gained special attention in reducing power consumption mainly in concern to digital logic design. The main aim of this paper is to realize and synthesize shift counters like Ring counter and Johnson ring counter using reversible logic. Shift Counter is a sequential circuit that performs counting through shifting operation in a loop fashion. The output of last register of the circuit will be fed to the input of first register. Ring counter owns its applications in clock division circuits, square wave generators, hardware logic design of ASIC and FPGA circuits etc., Ring counter and Johnson Ring counter are designed using logical reversible Computation to reduce heat dissipation or power consumption. A Boolean function f(i_1, i_2, i_3,......, i_n) having 'n' inputs and 'm' outputs is said to be logically reversible when its corresponding number of inputs are equal to the number of outputs (i.e. n = m) and when its input pattern uniquely maps the output pattern. Logical reversible computation has its applications in various fields like Quantum Computing, Optical Computing, low power VLSI etc., Logical reversibility has gained essence in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, shift registers like shift right register and shift left register which has less heat dissipation and low power consumption is proposed. Till to date shift counters are not yet designed using reversible logic. In this paper an attempt is made to design shift counters like ring counter and Johnson ring counter using reversible logic. The designed circuit are analysed in terms of quantum cost, garbage outputs and number of gates. The Circuits had been designed and simulated using Xilinx software.