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An Efficient, Current-Mode Full-Adder Based on Majority Logic in CNFET Technology

机译:基于CNFET技术的多数逻辑的高效,电流模式全加法器

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In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.
机译:在本研究中,提出了一种基于多数逻辑的新型高速低功率电流模式全加法器(CMFA)。所提出的CMFA仅由14个晶体管组成。通过Hspice使用32nm碳纳米管场效应晶体管(CNTFET)Stanford模型以0.5V,操作频率为1GHz的操作频率,2FF的负载电容和10μA的电流用于任何参考电流的仿真适用于低压高速应用的值。仿真结果表明,在最坏的情况下,所提出的总和和携带输出的延迟等于42 ps,电源延迟产品(PDP)为98.7 -17 j。

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