1-Tbyte/s 1-Gbit DRAM Architecture with Micro-pipelined 16-DRAM Cores,8-ns Cycle Array and 16-Gbit/s 3D Interconnect for High Throughput Computing

摘要

A novel DRAM architecture with an ultra-high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques: I) five-stage pipelined I 6-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, and 3) a 16-Gbit/s I/O circuit on each of 32 through-silicon-via pairs/DRAM core. We conducted a circuit simulation assuming a 45-nm I -Gbit chip and confirmed that the proposed architecture achieved a 1-Tbyte/s bandwidth with 19.5-W power consumption.