A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper)

摘要

This work proposes a simple method of calculating FD capacitance in 2-dimensional (2D) TCAD simulation that combines with pixel layout, simplifying the estimation of CIS FD design. Approximate per unit FD junction capacitance can be extracted by few TCAD simulations. This method has been verified using an image sensor chip with 10um-size pixel fabricated in 180nm CIS process. The testing results show that the error percentage of FD capacitance between test and calculation is approximately 5.90%.