A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset

摘要

In this paper, the transceiver which incorporates a PLL using a ring voltage-controlled oscillator (VCO), a phase interpolator (PI), the quarter-rate linear phase detector (PD) and an output driver with pre-emphasis is presented. The phase detector which uses a clock whose frequency is a quarter of the data rate and reduces the phase offset is proposed. The transceiver, implemented in a 0.18-μm CMOS technology, operates at 3.2-Gb/s over a 10-cm PCB line with the Bit Error Rate (BER) of less than 10−12. The chip area is 3.7 × 2.5 mm2 and the core without I/O consumes 45-mA and I/O buffers consume 80-mA from a 1.8-V supply.