Advanced Profile Control and the Impact of Sidewall Angle at Gate Etch for Critical Nodes

摘要

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control isviewed by many as the most critical application for integrated metrology on etch systems. For several years, integratedmetrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicongate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CDvariation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electricalperformance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficultyof measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement oflitho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible thatthe polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. Thispaper will examine the current relationship between litho and etch profile control, determine potential limitations forfuture technology nodes, and introduce novel etch process control techniques based on multiple input multiple output(MIMO) modeling.