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Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling

机译:用动态电压和频率缩放比例制定最佳测试计划问题

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Various techniques for modern high performance designs, such as clock gating and dynamic voltage frequency scaling (DVFS), have been adapted to address power issues. This is a consequence of technology scaling and it is important and desirable to address reliability needs as well as economic issues. From a testing point of view, introduction of power constraints during testing is needed for the desired product quality and to avoid yield loss. Unlike designers who have often benefited from the design for test hardware introduced for testing, test engineers have rarely taken advantage of the extra hardware introduced to meet design needs. In this paper, we make use of the DVFS technology and its associated hardware to improve test economics. We formulate the power constrained testing problem as an optimization problem that makes use of DVFS technology. We show that we can obtain superior test schedules for both session-based and session less testing methods relative to existing and traditional methods of obtaining test schedules.
机译:诸如时钟门控和动态电压频率缩放(DVFS)之类的现代高性能设计的各种技术已经适应解决电源问题。这是技术扩展的结果,解决可靠性需求和经济问题非常重要,也是人们所希望的。从测试的角度来看,为了获得所需的产品质量并避免产量损失,需要在测试过程中引入功率约束。与通常从设计用于测试的测试硬件中受益的设计人员不同,测试工程师很少利用引入的额外硬件来满足设计需求。在本文中,我们利用DVFS技术及其相关的硬件来提高测试的经济性。我们将功耗受限的测试问题表述为利用DVFS技术的优化问题。我们证明,相对于现有的和传统的获取测试计划的方法,我们可以为基于会话的和较少会话的测试方法获得更好的测试计划。

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