This paper presents the implementation of Orthogonal Triangular factorization based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA) using hardware software Co-design. The computation is carried out with help both hardware concurrency and software back substitution calculation. The system has been implemented on Altera Cyclone 4 FPGA with Embedded Nios- II soft core processor. The hardware part consists of a custom peripheral that solves the part of the algorithm with higher computational costs and the software part consists of an embedded soft core processor that manages the control functions and rest of the algorithm.
展开▼
