Understanding the Role of the Low Temperature Seed Layer in the Growth of Low Defect Relaxed Germanium Layers on (111) Silicon by Reduced Pressure CVD

摘要

There is currently significant technological interest in the epitaxial growth of high quality relaxed Ge layers directly on Si substrates for potential applications including: high-mobility metal-oxide-semiconductor field-effect-transistors (MOSFETs) [1], infrared photodetectors [2], solar cells and III-V integration [3]. Whilst the majority of research in Ge epitaxy has focused on its growth on (001)-oriented Si substrates, the potential for high mobility Ge channel MOSFETs on non-(001) Si substrates has already been predicted and demonstrated. For instance, the highest electron mobility value (~ 1920 cm2V-1s-1) in a Ge n-channel MOSFET was recently reported on a (111)-oriented substrate [4]. The large lattice mismatch (4.2 %) between Si and Ge can complicate the epitaxial growth resulting in three-dimensional islanding, surface roughening and a high density of threading dislocations penetrating the surface. Several approaches have been used to minimize these effects, including the use of surfactants [5] and growth of a low temperature (LT) seed layer prior to deposition of high temperature (HT) layers [6]. Thick (≥ 500 nm), fully relaxed Ge layers can now be grown with low threading dislocation density (TDD) values (~ 1 x 107 cm-2) and smooth surfaces (root mean square (rms) roughness values ≤ 1 nm) [7]. Epitaxial growth of Ge on (111)-oriented Si is further complicated because the strain-relieving 60° a/2 dislocations can dissociate into 90° and 30° Shockley partial dislocations, which can glide apart under the influence of different shear forces, resulting in the formation of extended stacking faults [8]. As a result, Ge layers grown on (111)-Si usually have much higher TDD and surface roughness values (≥ 10 times higher) than those layers grown on (001)-Si [9]. We have recently demonstrated the growth of thick (~ 500 nm), relaxed Ge layers on (111)-Si by reduced-pressure CVD with- significantly lower TDD (~ 2 x 108 cm-2) and rms surface roughness values (2.1 nm) than those that had previously been reported [9-10].We employed a thin (~ 10 nm) low temperature Ge seed followed by deposition of a high temperature layer and subsequent annealing at 830°C (Fig. 1). Moreover, we demonstrated that this method could significantly reduce the stacking fault density, to levels barely detectable by transmission electron microscopy (TEM). In this work, we will discuss the role of the low temperature seed layer in more detail, by analyzing layers grown at a range of temperatures and as function of layer thickness with a combination of analysis techniques including high resolution TEM, atomic force microscopy (AFM) and x-ray diffraction (XRD). The aim of the LT seed is to accommodate all of the lattice mismatch, leaving the HT layer fully relaxed. In practice there is some residual compressive strain which, as the growth temperature is increased for the HT layers, can lead to island formation at the start of these HT layers. These Ge islands can act as sources for further dislocation nucleation and promote dislocation annihilation within their restricted volume. This influences both the dislocation network during the growth and the surface morphology of the final high temperature layer. However, the continued high temperature growth leads to a smoothing effect as the mobile dislocations annihilate and a smooth surface of less than 2 nm rms, although the threading dislocations can also dissociate into stacking faults for (111) oriented growth leading to surface steps.