A Low Complexity and Programmable Encoder Architecture of the LDPC Codes for DVB-S2

摘要

We propose a low complexity and programmable encoder architecture of the LDPC codes for DVB-S2 standard, where 21 variations of LDPC codes are defined. The proposed LDPC encoder takes advantage of the features of the codes, that is quasi cyclic codes and irregular repeat-accumulator codes. The key issue for realizing low complexity is a quasi-cyclic encoder using RAMs instead of shift registers. We implemented a programmable encoder circuit which is applicable to all LDPC codes defined in DVB-S2 standard, achieving easy operation.