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FACTORS INFLUENCING THE THRESHOLD VOLTAGES OF METAL OXIDE CMOS DEVICES

机译:影响金属氧化物CMOS器件阈值电压的因素

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摘要

Scaling MOSFETs to improve performance results in higher gate leakage as the silicon dioxide gate dielectric becomes thinner. Furthermore, polysilicon depletion becomes a significant portion of the gate capacitance and limits the scalability of the overall capacitance. To address these issues, there has been much interest in replacing the silicon dioxide with a higher permittivity dielectric and the polysilicon with a metal gate electrode. Unfortunately, new materials can cause significant threshold voltage shifts that are unacceptable for CMOS devices. In this paper, we review the factors influencing the threshold voltages and discuss options for addressing the threshold voltage shifts.
机译:缩放MOSFET以提高性能导致较高的栅极泄漏,因为二氧化硅栅极电介质变薄。 此外,多晶硅耗尽变为栅极电容的重要部分,并限制了整体电容的可扩展性。 为了解决这些问题,对用更高的介电常数电介质和具有金属栅电极的多晶硅替换二氧化硅和多晶硅已经有很多兴趣。 不幸的是,新材料可能导致CMOS器件不可接受的显着阈值电压移位。 在本文中,我们审查了影响阈值电压的因素,并讨论用于解决阈值电压偏移的选项。

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