首页> 外文会议>Asia-Pacific Conference on Simulated Evolution and Learning >APPLICATIONS OF EVOLUTION ALGORITHMS TO THE SYNTHESIS OF SINGLE/DUAL-RAIL MIXED PTL/STATIC LOGIC FOR LOW-POWER APPLICATIONS
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APPLICATIONS OF EVOLUTION ALGORITHMS TO THE SYNTHESIS OF SINGLE/DUAL-RAIL MIXED PTL/STATIC LOGIC FOR LOW-POWER APPLICATIONS

机译:进化算法在低功耗应用中为单/双轨混合PTL /静态逻辑合成的应用

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We present single-rail and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay and power in an experimental 0.1μm and 0.13μm CMOS technologies as well as a 0.13μm floating-body partially depleted silicon-on-insulator (PDSOI) process. Our experimental results demonstrate that both single-rail and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as SOI CMOS technologies.
机译:我们呈现基于遗传搜索的单轨和双轨混合通晶体管逻辑(PTL)合成方法,并将结果与其在区域,延迟和电力方面使用商业逻辑合成工具合成的传统静态CMOS对应结果。 实验0.1μm和0.13μmCMOS技术以及0.13μm浮体部分耗尽的绝缘体(PDSOI)工艺。 我们的实验结果表明,使用所提出的混合PTL / CMOS合成方法合成的单轨和双轨混合PTL电路均优于其局部CMOS以及SOI CMOS技术的延迟和动力的静态对应物。

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