Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity

摘要

This paper proposes a layout constraint extraction for CMOS analog layout retargeting. In this approach, first, we extract fundamental circuits such as current-mirrors and differential-pairs from a given netlist. Second, regular structures such as arrays and rows are extracted from a given layout which was designed before. Finally, we generate layout constraint by matching the fundamental circuits and the regular structures. A retargeting case study is shown to apply our approach to a comparator design.