Feasibility Study of an Ultra High Speed Current-Mode SAR ADC

摘要

This paper presents the feasibility study of a low-power 5-bit synchronous current-mode SAR ADC primarily targeted for ultra high speed applications. The circuit uses a voltage-current converter at the front end and a current steering DAC. The discrete analog output is digitized by a latch and a standard SAR logic in feedback to process the information by using a binary search algorithm. The proposed scheme exploits the compatibility of SAR ADCs with advanced technology nodes and provides an excellent opportunity to achieve ultra high speeds. The circuit exhibits a sampling rate upto 4 GS/sec with a full scale differential current of 1 mA_(pk-pk) or differential voltage of 300 mVp_(k-pk). The proposed circuit is designed and simulated at the transistor level in a 28-nm CMOS process, achieves a figure of merit of 18.3 fJ/conv.-step and dissipates 2.35 mW with a 0.9 V supply voltage.