VLSI Defect Analysis and Yield Management using Interactive Wafer Map

摘要

VLSI fabrication (VLSI Fab) process is perhaps one of the world's most complex manufacturing process carried out under highly stringent parameters of man, machine & environment. Generally, a 'Wafer Lot' of 25 silicon wafers goes through about 500 steps in the process of fabrication. Each step can introduce 'Defects' on wafers. SCL's (Semi-Conductor Laboratory, India) in-house developed Defect Database Management System (DDMS) is essentially a Wafer Inspection and Review Data Management Tool that takes defect data generated from VLSI Inspection Stations, convert it into a standard data format and integrates it with Defect Images and Bit Maps. This integrated data is used for review, analysis, and evaluation of defects and to generate various reports which are useful for yield improvement. Wafer map generation is a process of generating a visually similar image to wafer for viewing defects. Through interactive Wafer map, user can view and analyze defects by visualization of defects and corresponding defect images on the map. Sampling can be done through interaction with map and defect data file for sampled defects can be retrieved in tool's format for further review.