Design and Implementation of a Reconfigurable Digital Down Converter for 4G Systems Using MATLAB and FPGA- A Review

摘要

With the rapid growth in the technology, the generations that are evolved involve 1G, 2G, 3G, 4G and 5G technologies. The Digital Down Converter (DDC) is one of the important parts of a 4G receiver system. Development of an efficient DDC architecture is highly important because the applications are increasingly demanding for high efficiency and less power consumption. In this paper, a reconfigurable ddc architecture is introduced which reduces the hardware resources used. It consists of a mixer, decimator and a FIR filter. The proposed architecture is compared with the existing architecture. Simulations can be performed using MATLAB and implementation is proposed on FPGA using Verilog or VHDL code. Verilog is widely used since it is user friendly and easily understandable. The proposed DDC reduces the gate density.