Design of an on-scribe-line 12-bit dual-slope ADC for wafer acceptance test

摘要

Advanced technology suffers from more severe local process variation and thus requires measuring sufficient process control monitoring (PCM) devices to provide reliable wafer acceptance test (WAT) results. Adopting a large-scale device array with multiplexers can measure more PCM samples at a probe without increasing the pad count. Integrating a high-resolution and robust analog-to-digital converter (ADC) with the PCM circuits to replace the high-end ATE further reduces the test cost. It also alleviates the parasitic effects and thus accelerates the test and enhance the measurement accuracy. However, the on-wafer ADC design for WAT needs to be placed within the scribe line of the wafer. This work proposes a 12-bit dual-slope ADC that meets all the requirements for the aforementioned WAT scenario. The proposed switched-capacitor implementation makes the ADC robust against PVT variations. A test chip has been designed and fabricated in 0.18um CMOS. The active area of the proposed ADC is only 57 um by 581 um which well fits the narrow scribe line. Measurement results show the DNL and INL values are within +1.04/-0.8 and +1.83/-1.72 LSB, respectively. The ADC totally consumes 4.6 mW when operates at 3.3V and 3.2 kS/s.