Gate replacement technique with thick Tox to mitigate leakage with zero delay penalty for DSM CMOS circuit

摘要

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Here a wide-ranging survey and analysis has been done for leakage reduction based on active as well as idle mode of operation. This paper proposes a novel approach, based on run time leakage reduction, where a logic gate having Worst Leakage State (WLS) is replaced by some variation of standard logic cell having minimum leakage with the same input vector. For this purpose oxide thickness (T) of standard logic cell is increased to 2nm which highly reduces the leakage current and simultaneously increase in the W/L ratio of transistor for zero delay penalties due to gate replacement of the circuit is done. Proposed approach is based on gate replacement technique for reducing leakage without technology modification of IC. The Proposed approach achieves 88.39% average reduction in leakage current as compared with the conventional circuit leakage current with zero delay penalties, while basic gate replacement technique gives only 69.3%.