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A LEAKAGE ESTIMATION AND REDUCTION TECHNIQUE FOR SCALED CMOS LOGIC CIRCUITS CONSIDERING GATE-LEAKAGE

机译：考虑漏路的标定CmOs逻辑电路的漏电估计和降低技术

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1. A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology [J] . Maryan Mohammad Moradinezhad, Amini-Valashani Majid, Azhari Seyed Javad Circuits, systems and signal processing . 2021,第7期

机译：22 - NM CMOS技术中静态逻辑门的漏电和短路功率降低的新电路级技术
2. An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits [J] . Rahman H., Chakrabarti C. IEEE transactions on circuits and systems. II, Express briefs . 2005,第8期

机译：减少比例CMOS电路泄漏的有效控制点插入技术
3. An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits [J] . H. Rahman, C. Chakrabarti IEEE Transactions on Circuits and Systems. II, Express Briefs . 2005,第8期

机译：减少比例CMOS电路泄漏的有效控制点插入技术
4. A LEAKAGE ESTIMATION AND REDUCTION TECHNIQUE FOR SCALED CMOS LOGIC CIRCUITS CONSIDERING GATE-LEAKAGE [C] . Hafijur Rahman, Chaitali Chakrabarti IEEE International Symposium on Circuits and Systems . 2004

机译：考虑闸门泄漏的尺度CMOS逻辑电路泄漏估计和还原技术
5. Performance tradeoff of leakage reduction techniques in nanoscale CMOS circuits. [D] . Koppa Venkataswamy, Santosh Kumar. 2009

机译：纳米级CMOS电路中减少泄漏技术的性能折衷。
6. Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model [O] . Omnia S. Fadl, Mohamed F. Abu-Elyazeed, Mohamed B. Abdelhalim, 2016

机译：具有实际门延迟模型的CMOS组合逻辑电路的准确动态功率估算
7. Design Techniques for Gate-Leakage Reduction in CMOS Circuits [O] . 2008

机译：CMOS电路中减少栅极泄漏的设计技术

A LEAKAGE ESTIMATION AND REDUCTION TECHNIQUE FOR SCALED CMOS LOGIC CIRCUITS CONSIDERING GATE-LEAKAGE

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