Back Gated Strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs for Improved Switching Speed and Short-Channel Effects (SCEs)

摘要

The present work focuses on Figure-of-merit (FOM) of strained-Si-on-Silicon-Germanium-on-Insulator (SSGOI) MOSFETs with back gate configuration in terms of drain-induced-barrier-lowering (DIBL) and subthreshold swing (S). The theoretical model is developed by solving the 2D Poisson's equation with suitable boundary conditions using evanescent mode analysis technique in both the strained-Si and relaxed Si_(1-x)Ge_x layers. We have studied the effect of buried oxide thickness on DIBL and subthreshold swing. The validity of analytical model is verified by using ATLAS?, a 2D device simulator from Silvaco.