In this work, Dopant Segregated Schottky Barrier (DSSB) and Schottky Barrier (SB) vertical silicon nanowire (VSiNW) diodes were fabricated on p-type Si substrate using CMOS-compatible processes to investigate the effects of segregated dopants at the silicide/silicon interface and different annealing processes on nickel silicide formation in DSSB VSiNW diodes. With segregated dopants at the silicide/silicon interface, VSiNW diodes showed higher on-current, due to an enhanced carrier tunneling, and much lower leakage current. This can be attributed to the altered energy bands caused by the accumulated Arsenic dopants at the interface. Moreover, DSSB VSiNW diodes also gave ideality factor much closer to unity and exhibited lower electron SBH (Φ_(Bn)) than SB VSiNW diodes. This proved that interfacial accumulated dopants could impede the inhomogeneous nature of the Schottky diodes and simultaneously, minimize the effect of Fermi level pinning and ionization of surface defect states. Comparing the impact of different silicide formation annealing using DSSB VSiNW diodes, the 2-step anneal process reduces the silicide intrusion length within the SiNW by ～ 5X and the silicide interface was smooth along the (100) direction. Furthermore, the 2-step DSSB VSiNW diode also exhibited much lower leakage current and an ideality factor much closer to unity, as compared to 1-step DSSB VSiNW diode.
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