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A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol

机译:快速确定芯片多处理器缓存间距离不一致的测试设计,实现MOESI协议

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The data coherence in the cache systems of CMPs (Chip Multi-Processors) is to be more accurate and reliable. In this work, we propose an effective solution to the issue through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length single cycle attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of processors' private caches realizing the MOESI protocol. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.
机译:CMPS(芯片多处理器)的缓存系统中的数据一致性是更准确可靠的。在这项工作中,我们通过引入高效的测试逻辑(故障检测单元)提出了有效的解决方案。测试设计基于蜂窝自动机(CA)的模块化结构。已经引入了SACA(单长度单周期吸引力蜂窝自动机)以确定处理器私人高速缓存的缓存行状态的不一致性,实现了MOESI协议。基于CA的简单硬件实现实现了在CMPS中的快速决定,以100%的准确度。

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