Low power 12bit 50KS/s R-C SAR ADC implemented based on mismatch analysis

摘要

A low power 12bit 50KS/s R-C SAR (successive approximation) ADC is presented in this paper. A R-C DAC structure and modified sample-hold circuit are presented. For the digits distribution of R-C DAC, the mismatch analysis of capacitors and resistances is emphasized because precision of SAR ADC primarily depends on its DAC. Reasonable layout design can decrease the R-C DAC mismatch. A 12-bit resolution is achieved in 7–5 digits distribution structure of SAR ADC which operates with 1.8V analog power and 1.8V digital power, is realized in 0.18μm CMOS 1P6M technology. The SAR ADC draws only 0.54mW of power and has a maximum conversion frequency of 50KS/s and SFDR of 81dB.