Implementations of Reconfigurable Logic Arrays on FPGAs

摘要

This paper presents a method to implement a reconfigurable logic array on an FPGA. To design circuits with 2-valued k-input LUTs, 2{sup}k-valued logic is introduced. Standard benchmark functions as well as symmetric functions are efficiently implemented by a logic array with 2{sup}k-valued variables. Number of products and number of bits to represent functions by the expressions with 2{sup}k-valued variables for k = 1, 2, 3, 4, and 5 are compared. Both sum-of-products expressions and EXOR sum-of-products expressions of 2{sup}k-valued logic significantly reduces needed FPGA resources, when 2 ≤ k ≤ 5. Experimental results for benchmark functions and symmetric functions are shown. Implementations of arrays with 16-valued variables on Xilinx and Altera FPGAs are also shown.