A high speed DES implementation with reconfigurable S-boxes for new emerging network applications based on FPGAs.

摘要

With the advent of public Internet reaches worldwide, securities issues will play a vital role in the present and future of communication and computer networks. The breadth of the Internet and its growth in popularity has positioned it as the external network of choice for connecting Intranets securely, both within and between corporations. Today's corporate networks are now evolving toward a collection of physically separated Intranets interconnected over the public Internet. Inter-corporation communication is now a business necessity. This new business model presents a need for high speed and flexible security platform implementations for the next generation Edge and Core network switches. Data Encryption Standard (DES) cryptosystem application in ATM, SONET, Fast Ethernet, and Gigabit Ethernet networks require high performance and flexibility to quickly change algorithm parameters such as S-boxes. Field Programmable Gate Arrays (FPGAs) provide an ideal system solution for a reconfigurable platform. Although there have been a few previous published reports on DES implementations on reconfigurable devices, there has been no systematic treatment of high performance architectural issues with reconfigurable parameters.; This thesis deals with the design and implementation of a core crypto engine based on a symmetric private-key cryptosystems DES with emphasis on high speed and reconfigurable S-boxes. Various architectural issues such as pipelining and nonpipelining techniques will be investigated with their effectiveness on DES. The core cryptosystem, is developed on a reconfigurable hardware platform based on FPGAs. FPGAs combine the flexibility of software solutions with the higher performance of the traditional hardware ASICs or full-custom VLSI devices. In the former case, the algorithm is fixed at the time of manufacturing. Reconfigurable logic provides a hardware solution to easily change any algorithm parameters such as S-boxes, Permutation ordering, or output representations.; The design architectures are described in Verilog Hardware Description Language. The designs are synthesized and mapped to the state of the art 0.18 μm 6-layer CMOS Xilinx VirtexE FPGA devices. FPGAs silicon area resource and timing measurements are provides for both non-pipelined and pipelined DES architectures.