Predicting CPU requirements with variability equations of ZF-SQRD and rake receiver in a DSP context

摘要

Establishing generalized variability equations of two applications to depict the number of cycles performed by a signal processor and exploring the impact of software pipelining in the prediction of this variability are the primary objectives of this paper. Secondly, comes the procedure in order to automate the profiling of the target algorithms implemented in C. In terms of variability, a first analysis of implementation results has been realized with Zero Forcing Sorted QR Decomposition (ZF- SQRD) algorithm. It has pointed up that grouping the results according to their diversity gain permits to achieve more general equations for prediction without lost of precision. A second analysis with the Rake Receiver brings out a linear changeability of the clock cycles relying on the number of fingers variations. Finally, a ratio around one of two was deduced for the CPU requirements between enabled and disabled software pipelining for the both applications.