SystemC validation of a low power analog CMOS image sensor architecture

摘要

In a context of embedded steady camera for video surveillance with high performance requirements and hard power consumption constraints, a low power CMOS image sensor architecture allowing sensor's acuity adaptation to the scene activity is considered. In this paper we present an original approach based on SystemC modeling to validate a complex analog SIMD architecture (i.e. highly parallel and programmable) and the implemented algorithm.