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A systolic array for sequence comparison based on two-logic-levels processing element

机译:基于双逻辑级处理元素的序列比较的收缩阵列

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In this work, we implement a dynamic programming (DP) algorithm for sequence comparison (SC) purposes. We aimed at obtaining a better compromise between the processing acceleration optimization and the hardware cost. A simplified edit distance (ED) calculation formula is used, where we introduce two new simplified logical equations based on this last formula. A systolic array (SA) based on our simplified processing element (PE) can compare sequences with a great length and a high processing frequency. Our system speed-up shows a gain varying between 13% and 142% compared to other systems, according to the considered FPGA family.
机译:在这项工作中,我们实现了一种动态编程(DP)算法,用于序列比较(SC)目的。我们旨在在加工加速度优化和硬件成本之间获得更好的折衷。使用简化的编辑距离(ED)计算公式,其中我们基于此最后公式介绍了两个新的简化逻辑方程。基于我们的简化处理元件(PE)的收缩阵列(SA)可以比较具有较大长度和高处理频率的序列。根据所考虑的FPGA家族,我们的系统加速显示与其他系统相比的增益不同于13%和142%。

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