【24h】

A Formal Model of Lower System Layers

机译:下系统层的正式模型

获取原文

摘要

We present a formal model of the bit transmission between registers with arbitrary clock periods. Our model considers precise timing parameters, as well as metastability. We formally define the behavior of registers over time. From that definition, we prove, under certain conditions, that data are properly transmitted. We discuss how to incorporate the model in a purely digital model. The hypotheses of our main theorem define conditions that must be satisfied by the purely digital part of the system to preserve correctness.
机译:我们介绍了具有任意时钟周期的寄存器之间的位传输的正式模型。我们的模型考虑了精确的时序参数,以及衡量性。我们正式定义了寄存器的行为随着时间的推移。从该定义来看,我们在某些条件下证明了数据被正确传输。我们讨论如何在纯数字模型中纳入模型。我们主要定理的假设定义了系统的纯数字部分必须满足的条件以保持正确性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号