A Compact Analytical Model and Electrostatic Performance Investigation of Multilayer Groove Gate SOI-MOSFET

摘要

A hot-carrier-reliability assessment of Silicon on Insulator (SOI) based multi-layer rectangular groove gate silicon on insulator (MLRGG-SOI) MOSFET has been done using Sentaurus TCAD simulator. The architecture integrates the merits of SOI and the recessed channel (RC) technique in to a conventional MOSFET. Further, the impact of structural design parameters and stack gate architecture are analyzed on the behavior of (rectangular groove gate silicon on insulator) RGG-SOI MOSFET. By using Poisson's equation a compact equation for threshold voltage in terms of minimum surface potential has been developed. For device validation few results of MLRGG-SOI structure are estimated with conventional RGG-SOI structure. The comparison interprets that the proposed architecture provides an improved analog performance with enhanced short channel effects (SCEs).