The Storage Structure of Convolutional Neural Network Reconfigurable Accelerator Based on ASIC

摘要

With the development of deep convolutional neural networks (CNNs), it can be achieved higher accuracy in many aspects, including computer vision, speech and natural language processing. Performance efficiency of CNN at the hardware level requires overcoming the large calculation-related problems, so memory bandwidth and power budgets, should be in economical limits. CNNs models also adopts different kernel sizes, depends on the application nature, therefore it is important for designed architecture to be reconfigurable. In this work, we propose a new high-performance multi-precision reconfigurable architecture (MPRA) and optimize it for recent CNNs using 3×3/5×5/7×7 convolution such as AlexNet, GoogLeNet and ResNet with 16-bit fixed and 8-bit fixed precision. The architecture synthesized on 65 nm CMOS technologies achieves average performance (GOPS) of 276.5 in 16bit×16bit and 1105.9 in 8bit×8bit mode, running at 640 MHz and 1 V with a power dissipation of 599 mW respectively. Compared to state-of-the-art designs, the proposed architecture achieves 2.36x energy efficiency, 2.4x to 6.8x area efficiency, and 16.3% to 27.4% higher computational efficiency for AlexNet benchmarked reference.