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High speed buffer devices on the base of push-pull current amplifiers

机译:推拉电流放大器基部的高速缓冲器设备

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摘要

Method of structural-functional organization of high speed buffer devices on the base of push-pull current amplifiers is considered. The importance and practical expediency of the creation of such types of voltage buffers for obtaining the low error of linearity and high operation speed is substantiated. Push-pull voltage buffers with the input amplifying stages and input current compensation are considered and analyzed. Analytical relations, describing static transfer characteristic, taking into account the circuit core parameters, are given. The components, leading to the linearity error occurrence are determined, ways of its reduction are shown. Voltage buffers with the decreased output resistance are suggested, for this purpose, push pull DC amplifiers are additionally introduced in the circuit, they have profound negative feedback. Computer simulation of the static and dynamic characteristics of the suggested schemes of the voltage buffers has been carried out, the comparative analysis of the results obtained has been performed, the possibility of the construction of high speed buffer devices on the base of push pull current amplifiers has been proved.
机译:考虑了推拉电流放大器基部的高速缓冲器设备的结构功能组织的方法。基本化了用于获得线性度低的低误差和高运行速度的电压缓冲器的创建的重要性和实际权宜之计。考虑和分析具有输入放大级和输入电流补偿的推挽电压缓冲器。给出了描述静态传递特性的分析关系,考虑到电路核心参数。确定导致线性误差发生的组件,显示其减少的方法。提出了具有降低的输出电阻的电压缓冲,为此目的,推动拉动直流放大器另外引入电路中,它们具有深刻的负反馈。计算机模拟的电压缓冲器的建议方案的静态和动态特性,已经进行了对比较分析的结果,在推拉电流放大器基部构建高速缓冲器装置的可能性已被证明。

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