Design and implementation of 2bit Vedic multiplier at 16nm using PTL logic

摘要

As the demand for high speed computations have increased, Vedic multipliers have been implemented in circuits. In this paper, a 2bit Vedic multiplier has been implemented using Pass Transistor Logic. The implementation of 2 bit Vedic Multiplier using PTL results in 59.63% power reduction and 42.07% reduction in delay as compared to CMOS design at typical value of 0.9V. The tool for implementation is ngspice. The implementation technology of the circuit is 16 nm.