RISC Controller with Multiport RAM

摘要

Most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer core. Here, the design of a RISC controller is presented that uses Multiport RAM (MRAM). In this MRAM design, two ports are available for read operation and one port for write operation. This architecture performs two simultaneous read operations. Due to its unique feature better speed of operation can be achieved. The design is implemented on field-programmable gate array (FPGA). This RISC is a 32 -bit controller. The proposed controller has 32-bit ALU, serial-in/serial-out ports, 32-bit general-purpose registers, The proposed controller is physically verified on Xilinx Spartan 3E Starter Board EPGA.